1. Field of the Present Invention
The present invention generrlly relates to the field of microprocessor based computers and more particularly to a device and method for sharing a peripheral between processors coupled to the peripheral via two distinct busses.
2. History of Related Art
Microprocessor based computer systems implement various peripheral devices to extend the capability of the system and to reduce the work load placed upon the system's central processing unit. These peripheral devices are coupled to the central processing unit over one or more peripheral busses. These peripheral busses have evolved over time as peripheral devices have become increasingly complex and increasingly fast. The Industry Standard Architecture (ISA) bus was developed in the relatively early stages of microprocessor based computing systems. While the ISA bus had numerous drawbacks that eventually necessitated the development of newer busses, a large number of peripheral devices and adapters designed according to the ISA specification are still prevalent in more modern systems. One of the drawbacks of the ISA bus was its relatively narrow (16bit) I/O address bus. Because only a small number of devices can be uniquely addressed with the ISA address bus, indirect addressing was implemented to expand the capability of ISA devices without altering the specification itself. In an indirect addressing scheme, a device may include multiple internal registers that are individually accessible to the outside world through a single index register, which is given a unique ISA address. The index register is written with a data field indicating which of the internal registers is to be addressed in a subsequent cycle. In the subsequent cycle, a data register, which also has a unique ISA address is read or written to store to or retrieve information from the internal register indicated by the index register.
Prior to the wide spread proliferation of local area networks and network servers, the two cycles required to implement in direct addressing with the ISA bus was an acceptable compromise to maintain compatibility with the enormous base of hardware and software drivers developed around the standard. In many network servers and other sophisticated machines, however, peripheral devices may be accessible from or shared by more than one bus. Sharing of a peripheral device, coupled with the multiple cycle addressing scheme utilized in ISA architectures can lead to improper operation if a processor on one bus is permitted to alter the contents of a shared peripheral's index register while a processor on another bus is attempting to modify or retrieve the contents of the peripheral's data register. Moreover, it is impracticable to address this problem by requiring a software revision to peripheral device drivers for every potentially problematic peripheral device. Accordingly, it is highly desirable to implement a solution for sharing a peripheral device that may require indirect addressing between multiple busses without significantly impacting the performance of the device or system and without requiring revision to existing peripheral device drivers.